Introduction

In chip verification, bigger isn’t always better — especially when your tools can’t keep up. One of our customers was working with exceptionally large, complex designs — sometimes exceeding a billion gates.

Their verification process had turned into a performance nightmare:

• Runtimes stretched into days
• Memory usage pushed hardware to its limits
• Tape-outs were delayed because verification couldn’t keep pace with design progress

They needed a solution that could match the scale of their ambition — and their silicon.

Challenge

Performance bottleneck with large designs

• The customer's designs are exceptionally large and complex, often containing hundreds of millions of instances. Their previous verification tool was a significant performance bottleneck, with excessively long runtimes and high memory usage that strained their computing resources and delayed tape-outs.

Zettabolt Solution

LPC’s novel architecture and algorithm

Results

• The LPC tool delivered a dramatic improvement in performance. With its efficient data structures and patented algorithms for handling power state tables, the LPC tool was able to handle their largest designs with significantly faster runtimes and lower memory consumption compared to their previous solution.
• Furthermore, the tool's multi-threading capabilities provided a near-linear performance speedup, allowing them to run more verification cycles in less time and with minimal memory overhead. This performance advantage was particularly pronounced in their most complex designs.